Real Time Solutions

Quick guide to Design for In Circuit Testability

Revision: X4

Last updated:7/7/2003

Author: Robert Nussbaum

Preliminary Document – not released

Purpose:

The purpose of this document is to supplement certain DFT/DFM guides and to provide a quick reference for interested parties to avoid the common errors/omissions that are encountered in all aspects of creating electronic assemblies that may hinder the development of an in-circuit test set.

Definitions:

Test point - a non-orthogonally obstructed landing, via or test pad. Obstructions include hardware, solder mask and overhanging components.

LAYOUT

TEST POINTS

• All test points (targets) should be on the solder side of the board, 0.25" from board edge tooling and hardware holes. Test points appearing on the topside of the board will require the use of a clamshell type of fixture. Test points too close to the edge of the board may be blocked by vacuum seal requiring the use of a hold-down gate. Test points too close to tooling holes cannot be accessed.
• The preferred CTC spacing of test points 0.100" with 0.082" or greater to stay in the proffered class. 0.050" is the absolute minimum CTC distance.
• Test pads should be 0.065" (minimum 0.035") in diameter. It is possible to hit 0.020” targets, but reliability cannot be guaranteed, and it is more expensive.
• SMD pads occupied by SMD parts are not test pads.
• SMD pads not occupied by SMD parts are risky at best as test pads. If this becomes necessary, special documentation stating that this has been done should be presented as well as assigning logical names to the individual pads. A common example of this is using the pads from an SMD header that was in the artwork for prototype debug, but has been deleted when moved to production. The stencil artwork should be adjusted to not place solder on these “test pads”. The convex surface may deflect the probe off the pad.
• When there are no other alternatives. Unmasked on solder side vias may be used as test pads. They must follow all test pad guidelines including those found under ELECTRICAL AND CAD. Test pads are preferred to unmasked vias. Vias masked on the solder (test) side may NOT be used.
• Connectors may be used as test points. Though-hole connectors mounted on the component side are preferred test points. All other configurations will have additional costs. Side access, top access, relieved bottom access and dual height access all require non-standard parts and machining.
• Logical names should be given to all test pads. This is not absolutely necessary, but it will help with all parties DRC’s. All points used as test pads (test pads, unmasked vias, through hole connections etc.) having logicals assigned to them is preferred. Only unmasked vias and test pads having logicals is considered minimal. It is possible to extract this data from gerber and/or CAD data, and then assign a “random name” to the feature, but this requires translation and with ever changing CAD systems, cannot be guaranteed to be glitch-free.

POWER NETS (NOT GROUND)

• One test point for every four active devices plus 2 pads for test access and power supply sense. Always round up. Six is the preferred minimum.

GROUND NETS

• One test point for every two active devices plus 2 pads for test access and power supply sense. Always round up. Six is the preferred minimum.

ELECTRICAL AND CAD

• Boards with split power planes must have separate net names for each plane.
• Where separate ground runs and/or planes are tied together at a point, either they must all have the same net name, or there must be a jumper declared in the CAD data. Ex: AGND trace is tied to GND plane at a single point (8 closely spaced vias). One of the vias is called VJ1 of type Jumper with pin 1 = AGND and pin 2 = GND. This is not preferred as the virtual jumper does not appear on the BOM and therefore looks like a no-load to the CAD system. By calling it VJ1 instead of J1 or JP1, we have created a unique prefix than can be searched for by a type of DRC. Also, if the VJx way is adopted, at least one test pad must be provided on each net.
• Aperture file (s) must be included with gerber files.
• Test pads need logical names in CAD data and gerber data.
• Clocks, resets, chip selects, chip enables, output enables and similar control pins of IC's must be controllable. Clocks can have a tri-statable oscillator or be buffered through a tri-statable device. Resets, chip selects, chip enables, output enables and similar control pins of IC's simply need a pull-up or pull-down rather than to be hard tied. They can also be buffered through a tri-statable device. This is a must when trying to disable one device to enable and test another. Devices must be able to be individually controlled. Special care must be given to achieve this on nets that contain more than one output pin, or on nets that control several components ie. resets, some clocks, master selects etc.
• Custom IC's in general need to be tri-statable and should have test vectors in some standard format.
• Provide test pads for unused input pins, and when possible unused output pins.

Board Fabrication and Tolerance

• Tolerance from any board datum to any test pad must not exceed 0.002".
• Assuming two tooling holes on the board (diagonal corners preferred), tolerance between tooling holes must not exceed 0.002".
• Tooling holes should not be plated.
• Tooling holes must be a minimum of 0.095" in diameter with the tolerance of +0.003", -0.000". Suggested size: 0.125" Suggested tol: +0.002", -0.000".
• Components mounted on the solder side should not exceed 0.25".
• 0.025” preferred, 0.125" minimum of the solder side board edge must be free of any components, test points and open vias to use a vacuum gasket instead of a hold-down gate.
• 0.025” preferred, 0.125" minimum surrounding the tooling holes must be free of any components, test points and open vias.

Other:

• Schematics should have page numbers and an alphanumeric grid that at least quarters the page. Some companies have the ability to place the Page-Alpha-Numeric string automatically into the CAD data or produce a report that indicates what page(s) the part appears on.
• "No-loads" or "Do not installs" should be documented together on the BOM.
• If "No-loads" or "Do not installs" are shown on the schematic, then they should be surrounded by a dashed box and accompanied by a note.
• Schematics should have a chart on the first page for last used and skips of reference designators. Any virtual jumpers or other virtual components should also appear on this page surrounded by a dashed box and accompanied by a note.
• If either/or parts are incorporated into the design, both parts should be in the CAD data and on the schematic. On the schematic there should be a dashed box surrounding the parts and a note explaining the variable configuration. The BOM should also reflect the multiple configurations, Ex: U25 or U26 could be installed. The preferred part is U25. U25 is qty 1 and there is a note saying that U26 may be substituted.